1. Field of the Invention
This invention relates to magnetic memory arrays and, more particularly, to data line configurations within magnetic memory cells.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magnetoresistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magnetoresistive materials to set and maintain information stored within individual magnetic memory cell junctions of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a magnetic junction, and differential resistance measurements to read information from the magnetic junction. In general, an MRAM circuit includes one or more conductive lines with which to generate magnetic fields such that the magnetization directions of one or more magnetic junctions of the MRAM circuit may be set. Consequently, in some embodiments, the conductive lines may be referred to as “field-inducing lines.”
Typically, the conductive lines are formed as substantially straight and uniform structures of metal spaced parallel and perpendicular to each other within a plane comprising the magnetic cell junctions. In other words, the conductive lines are generally arranged in series of columns and rows having magnetic junctions interposed at the overlap points of the conductive lines. In this manner, the circuit may include a plurality of memory cells arranged within an array. In some cases, the conductive lines may be referred to as “bit” and “digit” lines. In general, “bit” lines may refer to conductive lines that are used for both read and write operations of the magnetic junction. In most cases, the bit lines are arranged in contact with the magnetic junctions. “Digit” lines, on the other hand, may refer to the conductive lines spaced vertically adjacent to the magnetic junctions and used primarily during write operations of the array.
In general, an individual magnetic junction can be written to by applying current simultaneously along a bit line and a digit line corresponding to the particular magnetic junction. Such an individual magnetic junction may herein be referred to as a selected magnetic junction, or the magnetic junction intentionally targeted for a writing procedure. During the writing procedure, however, the multitude of other magnetic junctions arranged vertically adjacent to the bit line and the digit line corresponding to the selected junction will also sense current. Such magnetic junctions are herein referred to as half-selected junctions or disturbed junctions, since a magnetic field is induced about them from the bit or digit line used to program the selected magnetic junction. Even though a less effective magnetic field is applied to these disturbed cells, variations within the magnetic junctions may allow the magnetic field induced by one current carrying line to switch the magnetization directions of one or more of the disturbed cells. In this manner, the write selectivity of the array may be reduced. Write selectivity, as used herein, may refer to the relative difference (i.e., current margin) between the amount of current responsible for switching the magnetization of a disturbed cell and the amount of current needed to switch the magnetization of a selected cell. Consequently, a reduction in write selectivity reduces the tolerance of the current used to reliably switch selected cells without switching disturbed cells within an array. In some cases, the tolerance may too small, allowing a false bit to be unintentionally written to one or more of the disturbed cells and in turn, decreasing the functionality of the array.
In addition, the number of memory cells arranged within an array may be limited by the arrangement of the conductive lines spanning across the columns and rows of the array. In general, the voltage required to generate a desired amount of current along a conductive line increases as the length of a conductive line increases, due to the current-resistance (IR) drop along the line. Since it is desirable to limit the overall power requirements of an array and, therefore, the amount of current used to operate the array, the conductive lines are generally restricted in length. In addition, the maximum voltage that may be used to operate an array may be restricted by the voltage supply coupled to the array, independent of the length of the conductive lines. Consequently, the number of magnetic junctions within an array is limited. In some cases, such a restriction causes the desired number of cells for a memory chip to be arranged within multiple arrays. Such an arrangement of cells, however, undesirably occupies a larger area of the wafer, increasing the size of the chip. As a result, fewer chips may be fabricated on the wafer, causing fabrication costs to increase and production throughput to decrease.
Therefore, it would be advantageous to develop a magnetic memory array with a configuration that requires a smaller operation voltage than memory arrays which employ both bit lines and digit lines to write to magnetic cell junctions. In addition, it may be advantageous to fabricate a magnetic memory array with a reduced memory cell size. Moreover, it would be advantageous to develop a magnetic memory array with a configuration that increases the write selectivity of a magnetic memory array.